As the size of integrated circuit designs grow rapidly, synthesis of very large flat designs becomes expensive and time-consuming. The traditional way of dealing with these problems is through the introduction of hierarchy in the designs. Hierarchical designs can be created such that the individual pieces of the hierarchy are of a good size for synthesis and the number of pieces in the hierarchy is proportional to the size of the designs. Synthesis can be run separately on each piece of the hierarchy, and these jobs can be run in parallel to reduce the total run time. With hierarchical logic design, logic paths often span from one physical unit to another. The lower units of the hierarchy are referred to as children and the higher units are referred to as the parent. It is a common task to create a timing budget for each unit and initially apportion time between interconnected units so that the individuals or teams designing different units can design those units to meet expected timing constraints for the overall design.